This invention relates to multiplexed multi-channel high speed optical transmission systems, and more particularly to a technique for directly extracting and deriving a large amplitude timing signal from the received signal in such systems.
In very high speed multi-Gbit/s fiber optic transmission systems onto which plural data channels are time-division multiplexed, the usual first step to access the individual data channels at the receiving end is to recover the timing signal from the received signal for purposes of establishing synchronization, for separating the plural data channels, and for detecting the received data bits.
For the widely used pseudorandom non-return-to-zero (NRZ) signal format, the data spectrum is a broadband continuum which does not contain sufficient energy at the clock frequency. In order to generate a timing signal at the receiving end from such a data stream two major steps are required. First, nonlinear signal processing steps such as transition enchancement (differentiation/squaring, multiplication), and/or other nonlinear treatment of the received signal are necessary to generate a relatively weak "reference" clock signal. (See for example, "Digital PCM Bit Synchronizer and Detector", by A. E. Moghazi, G. Maral, and A. Blanchard, IEEE Trans. Comm., COM-28, pp. 1197-1203, August 1980.) In a second stage, filtering (for example, SAW [surface acoustic wave]filtering), amplification, phase comparison (for example, phase lock loop [PLL]), and hardlimiting are performed to condition the clock before it can be applied to a decision circuit. (See for example: "2 Gbit/s timing recovery circuit using dielectric resonator", by D. J. Millicker and R. D. Standley, 1987, Elect. Lett,. 23, pp. 738-739; "New proposal for Multigigabit/s Clock Recovery IC Based on Standard Bipolar Technology", by D. Wang and U. Langmann, 1987, Electr. Lett., 23, pp. 454-56; and Digest, OFC '89, by K. Runge, et al, paper # WN2, Houston, Tex., 1989.) Several methods of generating discrete clock components from the received signal are well developed and commercial high-speed clock recovery circuits are available for frequencies up to 2.4 Gbit/s rates and have been implemented in off-the-shelf Gbit/s transmission systems.
For very high-speed and multi-Gbit/s systems, the transmitted signal is constructed by time division multiplexing, in either the electrical or the optical domain, incoming lower speed channels. The signal on each incoming lower speed channel and the multiplexed signal generally has a return-to-zero (RZ) signal format. In the RZ signal format, each time-slot contains either a pulse of finite width (less than the width of the time-slot), representing a binary ONE, or no pulse, representing a binary ZERO. Multiplexing with the RZ format is the common approach in multi-Gbit/s communication systems to increase the network throughput and in fiber optic systems to take more efficient advantage of the vast fiber bandwidth. (See for example, "1.13-Gbit/s Lightwave Transmission System" by K. Y. Maxham, J. M. Dugan, M. A. McDonald, and C. R. Hogge, J. Lightwave Techn., Lt-5, No. 10, pp. 1510-1517, Oct. 1987; "Multi-Gbit/s Picosecond Optical Pulse Transmitter Experiment" by H. Izadpanah, and A. Albanese, 1988, Conf. Digest CLEO '88, Anaheim, CA, pp. 128-129; and "Optical TDM for Very High Bit-Rate Transmission", by R. S. Tucker, G. Eisenstein, and S. K. Korotky, 1988, J. Lightwave Techn,. LT-6, pp. 1737-1749.) With a pseudorandom RZ signal format, the multiplexed data stream spectrum contains some energy at the desired clock frequency. It is, however, fully embedded in the continuous part of the frequency spectrum of the data signal. Processing stages are thus required to "clean up" (i.e., rejection of the power in the continuous spectrum outside the immediate region surrounding the clock frequency) and to amplify the reference clock for the second stage of processing.
An object of the present invention is to modify, at the transmitter, the spectrum of the multiplexed pseudorandom RZ signal so as to enhance the discrete clock component while simultaneously depressing the continuous component at that frequency to allow the enhanced clock component to be used, at the receiver, as the "reference" timing signal. The aforenoted preprocessing stages in the receiver needed to produce a reference clock signal can then be eliminated.
A further object of the present invention is to directly obtain, at the receiver, from this discrete clock component, the necessary large amplitude clock signal without the conventional multipart second stage processing circuitry needed in the aforenoted prior art timing recovery circuits.
A feature of the present invention is that the signal processing steps for clock recovery at the receiver can be performed in a fewer number of stages leading to a reduction of the receiver design complexity and a concomitant reduction in overall receiver cost.